1. Field of the Invention
The present invention relates to a differential amplifier circuit including an offset adjustment circuit, and an electric charge control apparatus for charging a secondary battery using the differential amplifier circuit.
2. Discussion of the Background Art
Conventionally, an electric charge control apparatus that charges a secondary battery includes an electric charge current detection circuit to detect an electric charge current flown to the secondary battery as shown in FIG. 6. As shown, an electric charge current to be flown to the secondary battery flows into a resistance Rsen, and the resistance Rsen converts the electric charge current into a voltage. Specifically, a differential amplifier circuit 101, a PMOS transistor 102, and a plurality of resistances 103 and 104 collectively form a subtraction circuit and divide a both end voltage of the resistance Rsen to a voltage Vsen with reference to a ground. The voltage Vsen is then outputted. Specifically, the electric charge current detection circuit 100 converts an electric charge current to be supplied to the secondary battery into a ground reference voltage Vsen, and outputs the ground reference voltage. The electric charge control apparatus executes constant current electric charge to the secondary battery using the voltage Vsen.
When an offset voltage appearing in the differential amplifier circuit 101 varies, an electric charge current can't be precisely detected. Further, when constant current electric charging is executed while the resistance Rsen is minimized for the purpose of reducing heat generation, an electric charge current to be supplied to the secondary battery varies as a problem. Then, as shown in FIG. 7, a conventional differential amplifier circuit attempted to include a trimming adjustment circuit so as to adjust an offset voltage as described in the Japanese Patent Registration No. 2962246. Specifically, in the differential amplifier circuit 110 of FIG. 7, a parasitic offset voltage is adjusted by turning on and off a plurality of current flowing in route switches 116 and 117, as well as a switch line 119 that controls a resistance element line 118 as a trimming resistance.
For example, a method for adjusting an offset voltage when a polarity of a parasitic offset voltage, represented by a difference between voltages of differential input terminals 111g and 112g, is positive is executed as described below. Specifically, when a current flowing to a source of a PMOS transistor 112 is larger than that flowing to a source of a PMOS transistor 111, a switch 117 is open to be in a cut-off condition to limit a current flowing to the source of the PMOS transistor 112 (i.e., a current flowing to the source 114s of a NMOS transistor 114) in step 1. The switch 116, however, is closed and maintains a conductive state.
Then, when a switch line 119 is open from its end in turn to be a cut off condition, a resistance element joins a route of current flowing from the source 114s of the NMOS transistor 114 in turn. The parasitic offset voltage disappears when the resistance element is added in turn until a current flowing to the source 114s of the NMOS transistor 114 is equal to that flowing to the source 113s of the NMOS transistor 113. Specifically, the switch line 119 is turn off in turn from its end to be a cut off condition until the parasitic offset voltage disappears in the differential amplifier circuit in step 2. In this way, the offset voltage of the differential amplifier circuit in a positive direction can be adjusted by executing these steps 1 and 2 from the initial condition.
A voltage drop serving as an offset correction voltage Vadj created in the resistance element 118 after offset adjustment is executed is calculated by the following formula, when a current value of a current source 115 is i115, a resistance value of the resistance element line 118 after offset adjustment is executed is R118, and a performance of gate voltage versus drain current of each of the PMOS transistors 111 and 112 is substantially equal to that of each of the NMOS transistors 113 and 114 (in case a current direction is opposite);Vadj≈R118×i115/2
However, according to the offset adjustment circuit of FIG. 7, since the switch line 119 is turned off in turn from its end until the offset voltage disappears, while all of a plurality of unit resistances forming the adjustment resistance has the same resistance value and the minimum resolution of the offset adjustment voltage is necessarily generated, the resistance value is significantly small. Accordingly, when a range for adjusting the offset voltage is wide, a great number of unit resistances are necessarily connected serially, thereby a chip area is increased. When the number of unit resistances is decreased for the purpose of reducing a chip area, a resolution of the offset adjustment becomes rough, and precise offset adjustment becomes impossible. When the resolution is maintained, an adjustment range becomes narrower as a problem.
Further, it is well known that an adjustment resistance value is largely affected by a manufacturing process, and thereby largely varies. As shown in an adjustment circuit of FIG. 7, since such unevenness of manufacturing is neglected and due to such, the minimum resolution voltage for adjusting an offset voltage as well as a voltage adjustable range change. For example, when a resistance value decreasingly changes due to the manufacturing unevenness, the minimum resolution is maintained, whereas an adjustable offset voltage range becomes narrower. To the contrary, when a resistance value increasingly changes, a prescribed minimum resolution can't be likely obtained.
Further, when a value of a unit resistance is decreased in view of manufacturing unevenness while maintaining the adjustable offset voltage range, a number of the unit resistances increases, and accordingly, the chip area again increases as a problem. Further, as mentioned above, an adjustment resistance value after offset adjustment is executed changes due to change in temperature or time elapsing, a conventional offset adjustment circuit can't deals with these changes and results in creating an offset voltage.